Integrated optical devices (for example, photonic integrated circuits) for directly processing optical signals have become of greater importance as optical fiber communications increasingly replace metallic cable and microwave transmission links. Integrated optical devices can advantageously be implemented as silicon optical circuits having compact dimensions at relatively low cost. Silicon optical circuits employ integrated waveguide structures formed in a silicon layer of a silicon-on-insulator (SOI) substrate, forming a silicon photonic chip.
In some applications, the optical signal is injected in/extracted from the photonic chip in a near perpendicular fashion, with respect to the photonic chip substrate plane, by way of an optical coupler (for example, a grating coupler) formed in the silicon photonic chip for input-output of the photonic signal. When using the silicon substrate in such a coupling fashion, such as when coupling to an optical fiber, the optical fiber is mounted in near perpendicular fashion.
During manufacture of integrated optical devices, a large number of integrated optical devices are fabricated on a typical semiconductor wafer. As part of a rigorous manufacturing process, it may be helpful to measure optical loss or spectral response for quality control at the wafer level. Since optical loss in individual optical components is relatively low (for example, on the order of 0.015 dB per component), testing for loss is typically performed on a special purpose test structure (i.e., the test structure will not be functional for the customer) comprising a plurality of optical components daisy chained together to define a testing (reference) circuit. During testing, a known/reference optical input is injected into the test structure and the optical output is measured for comparison to the known/reference optical input. The overall loss of the testing circuit is determined and divided by the number of test optical devices included therein to determine an average device loss. If the determined loss is outside an acceptable range, the wafer is considered defective and removed from the manufacturing process.
One potential issue with testing individual devices at the wafer level is that optical inputs and outputs must be precisely aligned to accurately measure device loss. This alignment issue is worsened when an optical fiber array needs to be aligned with multiple outputs (due to the intrinsic misalignment within the array). This may cause the testing process to be quite long and difficult. Since this testing is done at the wafer level before singulation, this laborious effort could grow geometrically if each wafer includes multiple testing circuits. Indeed, this task can be exhaustive when each IC within a wafer includes a testing circuit.
There is a need for a better method of testing and associated supporting test apparatus.